--
-- DE2 (Cyclone-II) Entity for Interactive Project Game
-- Authors:
--      Abdulhamid Ghandour
--      Thomas John
--      Jaime Peretzman
--      Bharadwaj Vellore
--
-- Desc:
-- Avalon Interface for the Vision Block.
-- readdata has X co-ord in lower 16 bits
--          has Y co-ord in next  15 bits
--          has no_detect in MSB
--

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity avalon_vision is

port (
	-- Avalon Signals
	clk          : in std_logic;
	read         : in std_logic;
	chipselect   : in std_logic;
	readdata     : out unsigned (31 downto 0);
	
	-- Camera Signals
	master_clk   : out std_logic;
	pixel_clk    : in std_logic;
	line_valid   : in std_logic;
	frame_valid  : in std_logic;
	pixel_data   : in unsigned (9 downto 0);
	
	-- Board Signals
	threshold    : in unsigned (9 downto 0);  -- SW9 to SW0
	no_detect    : out std_logic              -- LEDG0
	);
end avalon_vision;

architecture toplevel of avalon_vision is

signal data_signal : unsigned (9 downto 0);
signal valid_green_signal : std_logic;
signal end_of_frame_signal : std_logic;
signal end_of_row_signal : std_logic;
signal no_detect_signal : std_logic;

component ci_pxl port(
        clk             : in std_logic;
        mclk            : out std_logic; 	-- Master CLK to Camera
        lval            : in std_logic;     -- Line Valid from Camera
        fval            : in std_logic;     -- Frame Valid from Camera
        pixclk          : in std_logic;     -- Pixel CLK from Camera
        datain          : in unsigned(9 downto 0);    -- Pixel Data from Camera
        dataout         : out unsigned(9 downto 0);
        valid_green     : out std_logic;
        end_of_frame    : out std_logic;
        end_of_row      : out std_logic
   );
end component;

component visionsystem port(
	clk : in std_logic;
	pixel_data : in unsigned (9 downto 0);
	valid_green : in std_logic;
	endofrow : in std_logic;
	endofframe : in std_logic;
	threshold : in unsigned (9 downto 0);
	xout : out unsigned (15 downto 0);
	yout : out unsigned (15 downto 0);
	no_detect : out std_logic
    );
end component;

begin

	CAMERA: ci_pxl port map(
		clk => clk,
		mclk => master_clk,
		lval => line_valid,
		fval => frame_valid,
		pixclk => pixel_clk,
		datain => pixel_data,
		dataout => data_signal,
		valid_green => valid_green_signal,
		end_of_frame => end_of_frame_signal,
		end_of_row => end_of_row_signal
		);
		
	VISION: visionsystem port map(
		clk => clk,
		pixel_data => data_signal,
		valid_green => valid_green_signal,
		endofrow => end_of_row_signal,
		endofframe => end_of_frame_signal,
		threshold => threshold,
		xout => readdata (15 downto 0),
		yout (14 downto 0) => readdata (30 downto 16),
		no_detect => no_detect_signal
		);
		
	readdata(31) <= no_detect_signal;
	no_detect <= no_detect_signal;
	
end toplevel;

		
		
